Z80 Microprocessor (M.AU280 хичээл үзэх хүүхдүүдэд зориулав).

Z80 CPU
􀂄Long life cycle over 30 year
􀂊Microchip PIC, Motorola 6805, Intel MCS51
􀂄Bus master/arbitration
􀂊Multiprocessor, DMA support
􀂄10 addressing modes
􀂄Various Interrupts
􀂊Maskable, Non-Maskable, Daisy chain
􀂄DRAM refresh circuit
􀂄Z8 Single chip instruction compatible

Programming
Language􀂊Machine Language : binary􀂊Assembly Language : Assembler•3 fields : Label, Operation/operand, comments•Pseudo Instruction : ORG, EQU, DB, DW, DS, END􀂊High Level Language : Compiler􀂄Assembly Language􀂊1. Register􀂊2. Memory, I/O Address Map􀂊3. Addressing ModesLabel

Assembler
Symbol􀂊A, B, C, D, E, H, L, AF, BC, DE, HL, IX, IY, SP 􀂊Z, NZ, C, NC, PO, PE, P, M􀂄Constant/Literal􀂄Directives􀂊ORG, EQU, DB, DW, DS, END􀂊Macro : savreg•Macro : Assembly time facility (Preprocessor)•Subroutine : Execution time facilityLD

Registers
Main Register : A, F, B, C, D, E, H, L
􀂊A (ACC) :
•holds the results of arithmetic or logical operations
•Input/Output with peripheral devices.
􀂊F (Flag) : indicates specific conditions for operations
•S (Sign) : 1(-)/0(+)
•Z (Zero) : 1(0)/0(others)
•H (Half carry) : 1(carry or borrow at bit 3), BCD operation
•P/V (Parity/Overflow)
–P (Logical operation): 1(1's Even parity)/0(Odd)
–V (Arithmetic operation): 1(overflow)/0(normal)
•N (Negation) -1(sub)/0(add)
•C (Carry) -1(carry or borrow at bit 7)

ADD A, B ( A ←A + B )􀂊A : Destination (Result), B : Source􀂊Flagaffected according to the result of the operationnot affected􀂄Alternate Register : A', F', B', C', D', E', H', L'􀂊EX AF, AF' •A ↔A', F ↔F'􀂊EXX •B ↔B', C ↔C', D ↔D', E ↔E',H ↔H', L ↔L'
General purpose Register 􀂊8 bit : B, C, D, E, H, L, B', C', D', E', H', L'􀂊16 bit : BC, DE, HL, BC', DE', HL'􀂄Special function Register : PC, SP, IX/IY, I, R􀂊PC (Program Counter)•holds the 16-bit address of the current instruction being fetched from memory. •automatically incremented after its contents have been transferred.•the new value is automatically placed in the PC when a program jump occurs.􀂊SP (Stack Pointer)•holds the 16-bit address of the current top of a stack (TOS).•the Stack is located anywhere in external system RAM memory. •The external stack memory is organized as a last-in first-out (LIFO) file. •pushed onto the stack from specific CPU registers (PUSH). •popped off of the stack to specific CPU registers (POP).
Special Function Register
􀂊Index Registers (IX/IY)
•hold a 16-bit base address used in indexed addressing modes.
•index register is used as a base to point to a region in memory.
•additional byte is to specify a displacement from this base.
•greatly simplifies the tables of data.
􀂊Interrupt Register (I)
•allows interrupt routines to be dynamically located anywhere in memory.
•stores the high order eight bits of the indirect address.
•the interrupting device provides the lower eight bits of the address.
􀂊Refresh Register (R)
•Used as the memory refresh counter when the DRAM is used for memory.
•The low order 7 bits of R is automatically incremented for each instruction fetch.

n: 8 bits immediate data
􀂄nn': 16 bits immediate data
􀂄d: displacement (8 bit : -128 ~ +127 )
􀂄e: effective address (8 bit : -128 ~ +127 )
􀂄r, r': A, B, C, D, E, H, L
􀂄ss: BC, DE, HL, SP
􀂄pp: BC, DE, IX, SP
􀂄rr: BC, DE, IY, SP
􀂄qq: AF, BC, DE, HL
􀂄b: 0, 1, 2, 3, 4, 5, 6, 7 (bits)
􀂄cc: Z, NZ, C, NC, PO, PE, P, M (conditions)

Instruction Types
8/16 bit Data Transfer (memory and register read/write)
􀂄Exchange, Block Transfer and Search
􀂄8 bit Arithmetic and Logical (16 bit Arithmetic)
􀂄General purpose Arithmetic (DAA, CPL, NEG)
􀂄CPU Control (CCF, SCF, NOP, HALT, EI, DI, IM)
􀂄Rotate and Shift
􀂄Bit Manipulation (SET, RESET, TEST)
􀂄Jump, Call, and Return
􀂄Input/Output

Instructions
8 bit Memory Read/Write􀂊LD A, (nn‘) A ←(nn’)􀂊LD (nn‘), A (nn’) ←A􀂄16 bit Memory Read/Write􀂊LD HL, (nn') L ←(nn’), H ←(nn’+1)􀂊LD (nn'), HL (nn’) ←L, (nn’+1) ←H􀂄PUSH qq􀂊PUSH HL (SP -1) ←H, (SP -2) ←L, SP ←SP -2􀂄POP qq􀂊POP HL L ←(SP), H ←(SP + 1), SP ←SP + 2

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